Speed Up RF Mixed-Signal Simulation Using Novel Hierarchical Fast Envelope Simulation

With the fast growing personal communication and electronic markets system-on-chip (SoC) and system-in-package (SiP) circuit design has become an indispensable area in EDA. SoC integrates different types of circuits including digital, analog, and RF contents on one chip. SiP assembles all the electronic components including digital ICs, analog ICs, RFICs, and passive components in one package. The design of SoC and SiP requires large amount of mixed-signal including RF simulation due to the integration of various types of functional blocks in one IC or package. It is a big challenge to efficiently and accurately simulate mixed-signal circuits including RF blocks. It is not only due to the different methodologies used for different blocks but also because of the complicated modulated signals consisting of high frequency carriers and low frequency basebands often presented in the RF blocks. Traditional transient simulation technologies are inefficient for RF signals since the time steps are limited by the high frequency carrier and long time duration is required due to the low frequency baseband. This problem can be solved by Cadence’s newly developed hierarchical fast envelope simulation. In this paper we present how fast envelope simulation techniques increase the efficiency of RF mixed-signal simulation; why hierarchical approach is important in simulating large-scale circuits; and how to use hierarchical fast envelope simulation in RF mixed-signal simulation.